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Biography

PhD, principal investigator and researcher in Machine Learning and embedded systems. Twenty-two years of industrial experience in software, FPGA & IC Design Engineering with Digital SoC / IP ASIC, FPGA and PCB design and test, training and customer support experience in various industries. Project manager, team and technical leader. Three years of External Examiner experience and 12 years of lecturing, research, and supervision experience.

Academic and Research Experience

  • Research assistant on a PhD project designing low power embedded hardware for the SeNDT project in Trinity College Dublin.
  • PhD Research, researching Micro-architectural Optimisations of Machine Learning Algorithms in FPGAs, ASICs and Embedded Systems for Power, Area Conservation.
  • Supervised several students on Machine Learning related theses.
  • Current research interests include Micro-architectural optimisations in hardware and low-level software of artificial intelligence and machine learning algorithms. These optimisations are primarily targeted to reduce power and gate count in FPGA and ASIC devices and increase performance in embedded low power IoT Edge devices.
  • Peer reviewer for IEEE Access, IEEE TVLSI, Elsevier Microelectronics, Journal of the Chinese Institute of Engineers.

Engagement and Collaboration

Research Funding

  • 2022, Horizon Europe HORIZON-CL5-2022-D3-01 call, “Flexibility from Energy Communities through replicable solutions to couple water and electricity, creating sustainable marketplaces for a vibrant cross-sector energy ecosystem" , result pending.
  • 2022, Science Foundation Ireland Innovation Challenge SFI Future Innovator Prize 2021.
  • 2022-2026, President’s EngCore Research Fellowship (PhD) – PI.
  • 2022-2026, President’s EngCore Research Fellowship (PhD) – Co-PI.
  • 2022-2026, President’s EngCore Research Fellowship (PhD) – Co-PI.
  • 2020-2022, Irish Research Council Employment Based Program – PI.
  • 2019-2021, President’s EngCore Research Fellowship (MSc) – Co-PI.
  • 2019-2021, President’s EngCore Research Fellowship (MSc) – Co-PI.
  • 2019: Enterprise Ireland Innovation Voucher: EDR 775 Nmictech Ltd.
  • Worked as a Research Assistant on a PhD research project at Trinity College Dublin, 2003-2004.
  • Sought industrial collaboration in an expression of interest for research proposals for the Microelectronics Circuits Centre Ireland (MCCI) call.

Current Research Students

2019-Present, Institute of Technology, Carlow-

  • Bovenizer, Christopher (2020-2022), IRC Employment-Based Program M.Sc., “Live, On-site Automation of Harvesting Equipment using Artificial Intelligence, Vision and Sensor Systems" , Institute of Technology, Carlow and Tanco Autowrap Limited.
  • Furlong, Ryan (2019-2021), President’s EngCore Research Fellowship M.Sc., “Development platform for Artificial Intelligence at the network edge" .
  • Connolly, Luke (2019-2021), President’s EngCore Research Fellowship M.Sc., “UAV obstacle avoidance" , Institute of Technology, Carlow.

Past research students

2019, Institute of Technology Carlow-

  • Brennan, Colm (2019), M.Sc. in Communications Technology Management, “How can Machine Learning be Applied to Maritime Data Information to Aid Targeted Patrolling by the Irish Naval Service?"

2006-2008, Trinity College Dublin-

Areas of Interest as a Supervisor include

  • ASIC and FPGA design
  • Electronics
  • Embedded Computing and Sensor systems
  • Machine Learning

Publications and Outputs

Peer Reviewed Journal Articles

Furlong, R., O'Brien, V., Garland, J., & Dominguez-Mateos, F. (2021). Metric Embedding Sub-discrimination Study. arXiv preprint arXiv:2102.03176.

Garland, J., & Gregg, D. (2020). HOBFLOPS CNNs: Hardware Optimized Bitsliced Floating-Point Operations Convolutional Neural Networks. PREPRINT (Version 1) available at Research Square DOI: 10.21203/rs.3.rs-866039/v1

Alam, S. A., Garland, J., & Gregg, D. (2021). Low-precision Logarithmic Number Systems: Beyond Base-2. ACM Transactions on Architecture and Code Optimisation (TACO) 18, 4, Article 47 (December 2021), 25 pages. DOI 10.1145/3461699

Garland, J. and Gregg D. (2018) ‘Low Complexity Multiply Accumulate Units for Convolutional Neural Networks with Weight-Sharing’, in ACM Transactions on Architecture and Code Optimisation (TACO), vol. 15, no. 3, August 2018, Article 31, pp. 1-24, DOI: 10.1145/3233300

Garland, J. and Gregg D. (2017) ‘Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks’, in IEEE Computer Architecture Letters, vol. 16, no. 2, pp. 132-135, July-Dec. 1 2017, DOI: 10.1109/LCA.2017.2656880

Book Chapters

Anderson, A; Garland, J; Wen, Y; Barabasz, B; Persand, K; Vasudevan, A; Gregg, D. (2019) Chapter 6, ‘Hardware and software performance in deep learning’ in ‘Many-Core Computing: Hardware and Software’, pp: 141-161, ISBN: 978-1-78561-582-5.

Garland, J. and Gregg D. (2017) ‘Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks’, in ‘ACACES 2017 Poster Abstracts’, pp. 53-56, HiPEAC, the European Network of Excellence on High Performance and Embedded Architecture and Compilation.

Conference Proceedings and Papers

Garland, J. and Gregg D. (2021) ‘HOBFLOPS CNNs: Hardware Optimized Bitslice-Parallel Floating-Point Operations for Convolutional Neural Networks’, Presented at the 21st Workshop on Compilers for Parallel Computing (CPC’2021) – Virtual Event

Garland, J. and Gregg D. (2019) ‘Low Complexity Multiply-Accumulate Units for Convolutional Neural Networks with Weight-Sharing’, talk at HiPEAC January 2019, Valencia, Spain.

Garland, J. and Gregg D. (2017) ‘Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks’, Poster presentation, HiPEAC ACACES 2017, Fiuggi, Italy.